• Nxp Input Devices Driver Download 64-bit
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1. Customizing The Device Tree
   1. Referencing nodes
2. Device Tree for NXP Based Modules
   1. i.MX 6 Based Modules
   2. i.MX 6ULL Based Modules
   3. i.MX 7 Based Modules
   4. i.MX 8 Family Based Modules
   5. i.MX 8X Based Modules
   6. i.MX 8M Mini Based Modules
   7. Vybrid Based Modules

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A Device Tree is a data structure describing a system's hardware. Some hardware is 'discoverable' by design (e.g. PCI buses or USB buses) while some is not (notably memory-mapped peripherals). In the latter case, an operating system executable (the OS kernel) is often hard-coded for one device type. To make an operating system portable across different devices, a description of the layout of each supported hardware configuration is required to ensure the correct drivers and configuration are used. The ARM world is very heterogeneous, each SoC vendor and each board vendor wire their hardware a bit differently. In some other architectures (e.g. x86), there is a standard interface between the board firmware (BIOS) and the operating system to communicate the hardware layout - for instance, ACPI on x86. To overcome this lack of hardware description, the ARM Linux Kernel uses device trees as the preferred format of hardware description beginning around kernel version ~3.2. Prior to this change, all details of how the hardware was wired was part of the platform/machine layer and hard-coded in C structs. This became complicated as more and more ARM SoC vendors and boards appeared. More in-depth information is available in the presentation of Thomas Petazzoni about device trees.

The device-tree is not only a data structure that describes the SoC's internal memory-mapped peripherals, but it also allows us to describe the whole board. Toradex, therefore, creates device trees for each module as well as each carrier board (given that the modules Linux BSP supports device tree, see table below). However, especially if a custom carrier board is built, it is likely that you as a customer need to modify the device tree too. This article provides information on how to do that.

Some of our Linux BSPs make use of device tree enabled Linux kernels. The device trees are part of the Linux kernel source code and located in the arch/arm/boot/dts/ folder. For instructions on how to obtain the Linux source code for each module, refer to the article Build U-Boot and Linux Kernel from Source Code.

See the module-specific device tree descriptions and additional/intermediate device on the Device Tree for NXP Based Modules.

Typically, a device tree is defined at multiple levels and composed of multiple device tree files. Device tree files (dts and dtsi) may include other device tree files known as includable device tree files (dtsi). In this manner, a board-level device tree file (dts) generally includes a SoC level device tree file (dtsi). To support the modular approach of Toradex products, our device tree files usually have three levels of inclusion: carrier board, module and SoC level. This is also reflected in the device tree file names, which are composed by the three levels: ${soc}-${module}-${board}.dtb

We provide a carrier board level device tree file (ie. eval-v3) that is compatible with our evaluation carrier boards. Due to the standardized hardware interfaces of the Colibri and Apalis modules, this device tree file often also works for other carrier boards (e.g. our evaluation board device trees do work on the smaller carrier boards like Iris or Ixora). However, a custom device tree may still be required for a custom carrier board to allow enabling non (Colibri/Apalis) standard devices such as secondary Ethernet or disabling unused devices (preventing unnecessary drivers from loading and reducing boot time).

Nxp Input Devices Driver Download 64-bit

The Linux kernel needs device tree binaries (*.dtb) to boot. These binaries are generated by the device tree compiler from the device tree source files. The compiler is part of the Linux sources and is automatically built if needed.The kernel build system provides the dtbs target which compiles all device trees which are compatible with the current kernel configuration.ARCH and CROSS_COMPILE must be set and the kernel must be configured before device tree binaries can be compiled.

By specifying a single device tree file, a specific device can be built.

Each supported hardware device has a compatible string. Along with the compatible property, the device-specific properties need to be specified. These properties are specified in the device tree bindings. The most important properties are compatible, reg, clocks, interrupts, and status. A memory-mapped device (UART in this case) looks like this:

• Device Tree anatomy

Nodes can be referenced using the ampersand (&) character and the label.

A more detailed description of the device tree data structure can be found at devicetree.org. Nxp motherboards driver download for windows 10 64-bit.

Before starting the customization please have a look at the exact device tree layout of the module you are using (see below). Then, a straight forward way to start is copying the file of the carrier board level device tree, e.g. by executing the following command from within the kernel source tree:

As a next step you need to extend the Makefile. Edit arch/arm/boot/dts/Makefile and insert vf610-colibri-my-carrier.dtb right after vf610-colibri-eval-v3.dtb:

The command make dtbs should now compile also this new device tree binary. We recommend altering only this carrier board level device tree using the techniques below.

Tip: The kernel build system writes the combined device tree to the drive, e.g. arch/arm/boot/dts/.vf610-colibri-my-carrier.dtb.dts.tmp. The combined dts file can be handy to debug what the actual device tree file will look like. The combined file is ultimately compiled into the device tree binary representation (*.dtb) which is used by the kernel to boot.

Overwriting properties

To overwrite a property, the node needs to be referenced using the ampersand character and the label. Later device tree entries overwrite earlier entries (the sequence order of entries is what matters, hence the include order matters). Typically the higher layers (e.g. carrier board device tree) overwrite the lower layers (e.g. SoC device tree) since the higher layers include the lower layers at the very beginning.

E.g. for USB controllers which are capable to be device or host (dual-role), one can overwrite the default mode explicitly using the dr_mode property:

Activating/Deactivating Devices

An important device attribute is the status property. It allows devices to be activated/deactivated. A lot of devices are specified in the SoC level device trees but are disabled by default. By referencing the base node (using the ampersand character and the label), the device can be enabled by any of the layers overwriting the status property.

Overwriting nodes

Entire nodes can be overwritten by simply redefining them. Like overwriting properties, latter definitions overwrite earlier definitions.

E.g. to overwrite the pin configuration of Vybrids UART2 (UART_B) overwrite the uart2grp node by simply redefining it in your device tree (this pinctrl specification is already defined in vf-colibri.dtsi, but with the CTS/RTS pins)

Delete properties or nodes

It is also possible to delete properties or even nodes using /delete-property/ or /delete-node/. The following example deletes the fsl,uart-has-rtscts property defined in the carrier board level device tree imx6qdl-colibri.dtsi:

To delete a node, use its name, e.g.

Aliases

The device tree allows some device types to be rearranged using aliases. This is useful for RTCs, for instance, since the first RTC device is used as the primary time source for the system. The primary time source should be assigned to the rtc0 alias (in this example we assign snvsrtc as the primary RTC, which is Vybrids internal RTC):

Referencing nodes

If resources of another device are required, a reference is used to connect the two devices. Typically this is used to assign resources such as interrupts, clocks, GPIOs or PWM channels to a device. Depending on the referenced device, a specific amount of parameters (cells) are necessary. The amount is defined in the -cells property of the parent device.

GPIO

A GPIO specification needs a reference to a GPIO node and one or more cells (arguments). The amount of cells is driver specific. It can be obtained from the device tree binding documentation or by looking at the GPIO controller node (a device which exports GPIO is marked with the gpio-controller property). The #gpio-cells property defines how many cells are expected. E.g. Vybrid's GPIO controller is defined as follows in vfxxx.dtsi:

This means that the GPIO need to be referenced using two cells, e.g.

This example assigns a single GPIO from the GPIO controller with the label gpio1 (referenced using the ampersand character &), and passes it the two cells with a value of 10 and GPIO_ACTIVE_LOW. The meaning/order of the cells depends on the parent device type. The parent device's device tree binding documentation should contain more information on that.

The NXP based modules share a common GPIO cells format (see Documentation/devicetree/bindings/gpio/gpio-mxs.txt and gpio-vf610.txt):

This explains the meaning of the two cells from the example above:

• The first cell (10) is the GPIO number within the referenced GPIO bank
• The second cell (GPIO_ACTIVE_LOW) specifies the GPIO polarity (GPIO_ACTIVE_LOW is a preprocessor macro defined as 1).

Interrupt

Also, the interrupt controller specifies the number of cells required. The SoC internal interrupts are already assigned to the peripherals in the SoC level device tree, hence those most often do not need further handling. For external devices often GPIOs are used as an interrupt source. To make GPIO's available as interrupt sources, the GPIO controllers node is also annotated with the interrupt-controller property:

Interrupts can be assigned in a similar fashion, however, instead of using the linked parent as part of the interrupt specification, the interrupt-parent property needs to be used:

This example assigns GPIO 10 of the GPIO bank represented by gpio1 as the interrupt of a device.

Pinmuxing

Almost all peripherals need signals multiplexed to external pins in order to operate. The Linux kernel introduced the pinctrl subsystem around 3.1/3.2 and has especially become important in the device tree world. The exact workings of pinctrl (muxing, pin configuration etc.) vary quite a bit between different SoC vendors; therefore, device tree bindings are not standardized across our modules. Refer to the module-specific sections below for how to define a pinctrl block for the module you are using.

However, assigning pins to a driver works with standardized bindings. Each pinctrl subnode needs to be assigned to a driver, otherwise, the pinctrl won't apply the settings on its own. How and how many pinctrl groups can be assigned to a device depends on the device driver used. Most drivers are documented in the kernel source under Documentation/devicetree/bindings/ (search using the compatible string). Most drivers do not have specific pinctrl requirements and a default assignment can be made using pinctrl-0 for the pinctrl reference and a property pinctrl-names with the name 'default', e.g.:

To verify that a certain pinctrl has been picked up by the driver and correctly applied, the debug information available via sysfs can be helpful:

Device Tree Bindings

The device tree bindings for most supported hardware devices are documented in the kernel source tree inside the folder Documentation/devicetree/bindings/. One can also read the latest version of them online at kernel.org. However, bindings might have been changed between the actual kernel version used and the one documented online; hence when in doubt, use the documentation in the source tree.

Another source of device tree bindings are those provided by other boards. The device tree folder arch/arm/boot/dts/ contains a vast amount of supported ARM boards which might make use of device tree bindings for already supported hardware.

i.MX 6 Based Modules

The modules Colibri iMX6S/iMX6DL share the same device tree binary, so do the modules Apalis iMX6D/iMX6Q. Click on the box to see the current version of the respective device tree file.

Pinmux (iMX6)

Pin configuration such as pinmux or drive strength is either set by pinctrl-imx6dl or the pinctrl-imx6q driver. The SoC level device trees define the base configuration and allow to extend entries through the iomuxc label.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/imx6dl-pinfunc.h or imx6q-pinfunc.h respectively). The macros consist of three parts, a prefix, the pad (or ball) name (as used in datasheets) and the alternate function name. Since each pad has multiple alternate functions, there are multiple macros for a single pad, all ending with a different alternate function. It is crucial to select the correct macro for the intended use (e.g. the macro which contains GPIO as an alternate function if the pad is going to be used as a GPIO).

The 5th and last cell of a pin muxing entry need to be provided as a number in the device tree. This last cell contains the pin settings typically in a hexadecimal notation. Additionally, the last cell's bit 30 is used to give the setting of the SION bit, bit 31 prevents the iomuxc from changing the pad control register (see here for details).

There are preprocessor define for commonly used default pin configurations (e.g. PAD_CTRL_HYS_PU).

The bitwise definition for the last cell is given by the registers of the i.MX 6 Input/Output Multiplexer Controller.

For further details see Chapter 4 of the Toradex Colibri or Apalis iMX6 datasheet or/and Chapter 36 of the NXP^®/Freescale i.MX 6 application processor reference manual.

i.MX 6ULL Based Modules

Both versions of the Colibri iMX6ULL modules (256MB without Wi-Fi and 512MB with Wi-Fi) share the same SoC-level device tree file (imx6ull.dtsi) and there are dedicated files to each module.

Pinmux (iMX6ULL)

The i.MX 6ULL SoC allows multiplexing pins through its Input/Output Multiplexer Controller (IOMUXC). Beside multiplexing pins, this controller allows also to set pin configuration such drive strength. There are two largely independent controllers: the IOMUXC and the IOMUXC LPSR (low-power pin controller). The SoC level device trees define the driver node for each of this controller which bind to the pinctrl-imx6ul driver and defines the labels iomuxc and iomuxc_lpsr to give lower-level device tree access to the node.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/imx6ull-pinfunc.h or arch/arm/boot/dts/imx6ull-pinfunc-lpsr.h respectively), only the last cell need to be provided. This last cell contains the pin settings in a hexadecimal notation. Additionally, the last cell's bit 30 is used to give the setting of the SION bit, bit 31 prevents the iomuxc from changing the pad control register (see here for details). Since i.MX 6ULL SoC shares pin assignments with the i.MX 6UL SoC, various pin assignments for both processors are in the file arch/arm/boot/dts/imx6ul-pinfunc.h, which is included to arch/arm/boot/dts/imx6ull-pinfunc.h.

The bitwise definition for the last cell is given by the PAD Control Registers of the i.MX 6ULL Input/Output Multiplexer Controller.

For further details see Chapter 4 of the Toradex Colibri iMX6ULL datasheet or/and Chapters 4 and 32 of the NXP^®/Freescale i.MX 6ULL application processor reference manual.

i.MX 7 Based Modules

The modules Colibri iMX7S/iMX7D use independent device tree binaries, but due to the high intersection, most of the logic is in shared device tree source files.

Pinmux (iMX7)

The i.MX 7 SoC allows multiplexing pins through its Input/Output Multiplexer Controller (IOMUXC). Beside multiplexing pins, this controller allows also to set pin configuration such drive strength. There are two largely independent controllers: the IOMUXC and the IOMUXC LPSR (low-power pin controller). The SoC level device trees define the driver node for each of this controller which bind to the pinctrl-imx7 driver and defines the labels iomuxc and iomuxc_lpsr to give lower-level device tree access to the node.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/imx7d-pinfunc.h or arch/arm/boot/dts/imx7d-pinfunc-lpsr.h respectively), only the last cell need to be provided. This last cell contains the pin settings in a hexadecimal notation. Additionally, the last cell's bit 30 is used to give the setting of the SION bit, bit 31 prevents the iomuxc from changing the pad control register (see here for details).

The bitwise definition for the last cell is given by the PAD Control Registers of the i.MX 7 Input/Output Multiplexer Controller.

For further details see Chapter 4 of the Toradex Colibri iMX7 datasheet or/and Chapter 8 of the NXP^®/Freescale i.MX 7 application processor reference manual.

i.MX 8 Family Based Modules

Pinmux (i.MX 8 Family Based Modules)

The i.MX 8 family SoCs allow multiplexing pins through its Input/Output Multiplexer Controller (IOMUXD). Beside multiplexing pins, this controller allows setting pin configuration such as drive strength. The SoC level device trees define the driver node for this controller.

All pinmuxing/drive strength etc. is controlled in the System Controller Unit, a dedicated M-Core running the System Controller Firmware (SCFW). Linux's IOMUXC driver has no direct access to IOMUXC registers but uses the SCU driver to communicate with its firmware (SCFW).

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Integers need to be assigned to the property, each pin requires 3 integers. However, the first two are usually given by a #define (see include/dt-bindings/pinctrl/pads-imx8qm.h). With this define the SoC pin and its desired function is specified. In the example down below for example the pin FLEXCAN0_TX is muxed to the function DMA_FLEXCAN0_TX.

The third integer then defines the pin settings in hexadecimal notation. On the example below 0x21 means that Bit 0 and Bit 5 is set. Bit 0 sets high or low drive strength in this example with 1 meaning low drive strength. With Bit 6-5 the pull-up or pull-down behaviour is controlled with '01' meaning pull-up.

For a detailed description and table of possible pin-settings, look them up in the Reference Manual for the i.MX 8 family. At the time of writing this, the chapter for FLEXCAN0_TX pin settings was located at chapter 9.2.5.1.160.4

The possible muxings can be found in chapter 4 in the datasheet or with our Pinout Designer pinout.torizon.io.

Note: The meaning of these bits depends on the pin and has to be looked up for every pin in the Reference Manual. Thus we can not give a table here.

i.MX 8X Based Modules

• iMX8X Modules

  

Pinmux (i.MX 8X Based modules)

The i.MX 8X SoC allows multiplexing pins through its Input/Output Multiplexer Controller (IOMUXD). Beside multiplexing pins, this controller allows setting pin configuration such as drive strength. The SoC level device trees define the driver node for this controller.

All pinmuxing/drive strength etc. is controlled in the System Controller Unit, a dedicated M-Core running the System Controller Firmware (SCFW). Linux's IOMUXC driver has no direct access to IOMUXC registers but uses the SCU driver to communicate with its firmware (SCFW).

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Integers need to be assigned to the property, each pin requires 3 integers. However, the first two are usually given by a #define (see include/dt-bindings/pinctrl/pads-imx8qxp.h). With this define the SoC pin and its desired function is specified. In the example down below for example the pin FLEXCAN0_TX is muxed to the function DMA_FLEXCAN0_TX.

The third integer then defines the pin settings in hexadecimal notation. On the example below 0x21 means that Bit 0 and Bit 5 is set. Bit 0 sets high or low drive strength in this example with 1 meaning low drive strength. With Bit 6-5 the pull-up or pull-down behaviour is controlled with '01' meaning pull-up.

For a detailed description and table of possible pin-settings, look them up in the Reference Manual for i.MX 8X. At the time of writing this, the chapter for FLEXCAN0_TX pin settings was located at chapter 9.2.5.1.115.4.

The possible muxings can be found in chapter 4 in the datasheet or with our Pinout Designer pinout.torizon.io.

Note: The meaning of these bits depends on the pin and has to be looked up for every pin in the Reference Manual. Thus we can not give a table here.

i.MX 8M Mini Based Modules

• i.MX 8M Mini Modules

Pinmux (i.MX 8M Mini Based modules)

The i.MX 8M Mini SoC allows multiplexing pins through its Input/Output Multiplexer Controller (IOMUXD). Beside multiplexing pins, this controller allows setting pin configuration such as drive strength.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Integers need to be assigned to the property, each pin requires 6 integers. However, the first 5 are usually given by a #define (see arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h). With this define the SoC pin and its desired function is specified. In the example down below, for example, the pin GPIO1_IO06 is muxed to the function GPIO1_IO06 (Which is pretty obvious but GPIO1_IO06 could also be muxed to USDHC1_CD_B with the define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B for example).

The third integer then defines the pin settings in hexadecimal notation. On the example below 0x1c4 means that Bit 2, 6, 7 and Bit 8 are set. With Bit 0-2 one can set the drive strength. In this example, only Bit 2 is set which is meaning drive strength X2. Bit 6 means 'Select pull-up resistors', Bit 7 'Select Schmitt input' and Bit 8 'Enable pull resistors'.

For a detailed description and table of possible pin-settings, look them up in the Reference Manual. At the time of writing this, the chapter for PAD_GPIO1_IO06 pin settings was located at chapter 8.2.5.166.

The possible muxings can be found in chapter 4 in the datasheet or with our Pinout Designer pinout.torizon.io.

Vybrid Based Modules

The device tree files for the Colibri VF50/VF61 modules are quite similar, hence the common device tree nodes have been factored out to vf-colibri.dtsi and vf-colibri-eval-v3.dtsi. Click on the box to see the current version of the respective device tree file.

A device tree for a custom carrier board can also implement this extra dtsi for the common nodes between Colibri VF50/VF61. If the carrier board will only use Colibri VF50 or only Colibri VF61 anyway, the nodes of the common device tree file (vf-colibri-eval-v3.dtsi) can also be included in the main carrier board device tree (e.g. vf500-colibri-eval-v3.dts).

Nxp Input Devices Driver Download Windows 7

The Vybrid default boot scripts in U-Boot load the device tree file by combining multiple environment variables: ${soc}-colibri-${fdt_board}.dtb. The soc environment variable is detected according to the module type the boot loader runs on (vf500/vf610). The fdt_board is a static environment variable set to eval-v3 by default. If you provide your own carrier board device tree, you can make use of this environment variable to select the correct device tree:

Pinmux (Vybrid)

Pin configurations such as pinmux or drive strength settings are defined by the pinctrl-vf610 driver. The base device tree vfxxx.dtsi defines the base configuration and allows these entries to be extended through the iomuxc label.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/vf610-pinfunc.h), only the last cell needs to be provided. This last cell contains the pin settings in a hexadecimal notation.

The bitwise definition for the last cell is given by the registers of Vybrids Input/Output Multiplexer Controller. Refer to the following table for their meaning:

For further details see Chapter 4.2 of the Colibri VFxx datasheet or/and Chapter 6 of the NXP^®/Freescale Vybrid reference manual.

GPIO (Vybrid)

On Vybrid almost all pins can be used as a GPIO. To be able to use a pin as a GPIO, a valid GPIO pinmux must be present in the device tree. Our default device tree contains such a pinmux entry for all pins which are defined as being a GPIO by default (refer to the datasheet). For the other pins, make sure no driver is requesting them and create a proper pinmux configuration according to the Pinmux chapter.

There are 5 GPIO ports on Vybrid, represented by the node references gpio0 through gpio4. Each of which can address up to 32 GPIOs. Which GPIO port is used is defined by the GPIO node reference, the GPIO number within the port is the first cell. The assignment of the to Colibri pins to the GPIO blocks/numbers can be found in the Colibri VFxx Datasheet, Chapter 4.4 List Functions, GPIO port column. The GPIO polarity cell needs to be chosen according to the drivers/electronics needs. There are also preprocessor macros which can be used instead of the numbers (GPIO_ACTIVE_HIGH/GPIO_ACTIVE_LOW).

E.g. to reference the pin Colibri SO-DIMM 133 (according to the Colibri VFxx Datasheet connected to Vybrids PORT2[24]) one needs to use this GPIO specification:

Note: Vybrid starts counting its GPIO banks with 0, hence the first bank is available under the label gpio0.

User-space

To use a SO-DIMM as GPIO using the sysfs interface (see GPIO (Linux)), a valid pinmux configuration is required. Most GPIOs have a valid configuration in the vf-colibri.dtsi device tree under the node additionalgpios.

If there is no pinmux for the pin in question, the sysfs layer will respond with a 'Invalid argument' error:

In this case, add a Pinmux entry as described above.

In case the pin is already in use by a different driver, the error code would be 'Device or resource busy'.

Make sure the SO-DIMM pin in question is not in use by any driver. In case a driver is referencing it, you can disable the driver.

Device Tree Overlays (DTOs) provide a way to modify the overall device tree without re-compiling the complete device tree. Overlays are small pieces or fragments of an entire device tree. They can be added or removed as needed, often enabling/disabling hardware components in the system.

Device Tree Overlays were introduced in BSP 5. Therefore this information does not apply to earlier BSPs.

See the Device Tree Overlays article, for specific information.

The examples are collected in a separate article: